1. Field of the Invention
The present invention relates to sampling of data signals in a transmission system, and more particularly, to sampling data to ensure that a meta-stable condition is avoided.
2. Related Art
Many applications require synchronization of data across two different clock domains. Conventional art uses simple resample techniques that employ registering a lower frequency clock signal using a higher frequency clock signal. A logical combination of final output stages generates an edge that is synchronous with either the rising or falling edge of the faster clock. In this way, the edge can be used to enable the transfer of data from the slower clock domain to the faster clock domain. This prevents data from being sampled at a time coincident with the time when the data is changing. Use of this technique prevents what is called a meta-stable condition. An unavoidable side effect of this type of data synchronization is an additive “jitter” or sample uncertainty equal to one period of the faster sample clock.
In one embodiment of a standard DOCSIS application, the master clock is typically 163.84 MHz. This clock is often used to generate other clocks for other purposes. Specifically, the master clock of 163.84 MHz is divided by 2 to generate a 81.92 MHz clock used for sampling data. It is also divided by 8 to generate a 10.24 MHz data clock. Thus, one clock reference (163.48 MHz) is used to generate multiple synchronous clocks (81.92 MHz, 10.24 MHz).
However, a particular problem arises in that as between a transmitter and a receiver, even though the frequencies of the clocks are known, the phase relationship between the data sampling clock (hereafter referred to as CLK2) and the data clock (hereafter referred to CLK1) is often unknown. Thus, while the two time domains have clocks in a coherent relationship with each other, their phase relationship is not known. This can give rise to a condition known as meta-stability. If a receiver tries to sample the data stream on a data transition, the value of the data at the transition point is undefined. This can result in a loss of data and loss of synchronization, which is unacceptable in a transmission system such as an SCDMA transmission system.
When two coherent clock sources are used, the problem of additive “jitter” can be avoided if the phase relationship between the two coherent clock sources is known. If the phase relationship is not known—or cannot be predicted with certainty—then the problem of synchronizing data from the slower clock domain to the faster clock domain must take into account the possibility of a meta-stable sampling of data. When designing for this scenario, then, “jitter” is also a possibility due the unknown phase relationship between the clocks.